+86 21 34616270
info@sitchip.com
徐汇区裕德路168号徐汇商务大厦619室
  • 关于芯桥
  • 新闻
  • 解决方案
  • 产品
    • Synopsys
      • Galaxy平台
      • Design Ware IP
      • Discovery平台
      • System-level Design & Analysis
    • CEVA
    • Arteris
    • VeriSilicon
    • Vivante
    • SILEXICA
  • 服务与培训
    • 专业服务
    • 培训安排
  • 合作伙伴
    • Synopsys
    • CEVA
    • Arteris
    • VeriSilicon
    • Vivante
    • SILEXICA
  • 人才招聘
  • 联系我们
  • About SIT

Arteris

首页 产品 Arteris
674arteris_logoThe Network-on-Chip Company 

Fact Sheet

Founded:
February 2003

Headquarters:
Silicon Valley, CA, U.S.A.

Products:
Network-on-chip interconnect fabric IP for SoCs

Arteris provides Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) to System on Chip (SoC) makers so they can reduce cycle time, increase margins, and easily add functionality. Arteris invented the industry’s first commercial network on chip (NoC) SoC interconnect IP solutions and is the industry leader. Unlike traditional solutions, Arteris interconnect plug-and-play technology is flexible and efficient, allowing designers to optimize for throughput, power, latency and floorplan.

Arteris is different because we were founded by networking experts who applied their knowledge to the problems of SoC development. As SoC makers added more IP blocks to chips, traditional bus and crossbar means to communication became very inefficient, resulting in serious pain to architects, designers, and integrators: Massive numbers of wires,failed timing closure, increased heat and power consumption, and spaghetti-like routing congestion leading to increased die area. These problems were compounded when there were IP changes late in the design cycle or when management expected the next derivative version of the chip to be on time and risk free because only a few IP blocks were changed.

Arteris On-Chip Interconnect Technology

The Arteris Network-on-Chip (NoC) architecture borrows concepts from the computer networking arena and adapts them to system-on-chip design constraints. The network on chip solution optimizes performance, silicon area, and power, and reflects an in-depth understanding and integration of the constraints imposed by SoC implementations and semiconductor processes. By removing the inherent architectural limitations of traditional interconnect solutions, Arteris Network-on-Chip semiconductor IP offers a quantum leap in design quality and productivity, allowing SoC designers to achieve their ultimate design goals faster, easier and with less cost.

Arteris pioneered the first commercial NoC SoC offering, led the mass market adoption of Network-on-Chip solutions, and is the market leader in this space. There have been over 50 tapeouts of systems-on-chip using Arteris network-on-chip interconnect IP.

Key benefits of Arteris network-on-chip interconnect solutions include:

  • Improved performance, power and silicon area
    • Fewer Wires and Lower Routing Congestion allows decreased SoC area and power density while maintaining shorter schedules
    • Highly Flexible Timing Convergence and Timing Closure improves frequency and performance in much fewer iterations than traditional methods
  • Highly scalable to support a wide range of performance and complexity levels
    • Easy-to-use solution for simple designs with a handful of IPs to complex SoCs with hundreds of IPs
    • Plug-and-Play with IP using any transport protocol – no IP lock-in
  • Shortened development times with advanced tool suite and architecture features
    • Architect-centric tools allow architects to increase their efficiency and value-add to the entire design team
    • Providing certainty in tape out schedule by allowing faster and easier verification and timing closure

Arteris operates globally with headquarters in Campbell, California, in the heart of Silicon Valley. Arteris is a private company.

近期文章

  • Synopsys推进虚拟原型技术可支持系统和半导体供应链合作缔造下一代SoC
  • 展讯公司采用Synopsys的ZeBu Server硬件加速器作为其高级移动SoC的标准化开发平台
  • Socionext使用Synopsys TetraMAX II加快测试向量生成并降低测试成本
  • 2016 Synopsys SNUG China(上海站)五月隆重开幕【欢迎报名】
  • Silexica 诚邀您共同迎接多核技术挑战
  • Synopsys SIT Silicon to Software成都研讨会
  • Synopsys推出高性能嵌入式视觉处理器IP
  • Ramon 公司采用CEVA DSP 核 设计空间应用抗核辐照高性能并行处理器
  • Synopsys推出高性能嵌入式视觉处理器IP
  • 新思科技Synopsys虚拟原型设计专著发行超3000本,读者覆盖超1000家公司


上海芯桥信息技术有限公司 SiT (Shanghai) Co., LTD
沪ICP备12038304号