CEVA-X1643 DSP core for Multimedia Applications, Wireless Baseband, and more
CEVA-X1643 Block Diagram
The CEVA-X family of cores is based on a unique mix of Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) architectures. The VLIW architecture allows a high level of concurrent instructions processing, thereby providing extended parallelism and low power consumption. The SIMD architecture allows single instructions to operate on multiple data elements, thereby resulting in code size reduction and increased performance. This processor family offers best-in-class performance, scalability, ease of programmability at the C level, and the flexibility to support a wide variety of applications. The CEVA-X family offers an architectural framework from which multiple DSP designs are derived. Each DSP design is aimed to serve different application needs characterized by performance, power consumption, and cost.
The most recent member of the CEVA-X family, the quad-MAC, 8-way VLIW CEVA-X1643 DSP core, offers a fully cached memory subsystem and higher power efficiency.
CEVA-X1643 Target Applications
Target applications for the CEVA-X1643 include 3G/4G baseband processing, wireless communications, multimedia applications, surveillance systems, mobile devices, and more.
| Features | Benefits |
|---|---|
Advanced VLIW + SIMD architecture offering very high ILP (Instruction Level Parallelism)
|
Optimal for demanding DSP applications in various markets |
High performance
|
Meets the power, cost and frequency requirments of next generation SoCs |
Easy software development
|
Smooth C-level software development and easy integration into the target SoC reduces risk and time-to-market |
Energy Efficient Interated Power Scaling Unit (PSU) supporting:
|
Highly power efficient optimized for mobile devices |
Advanced memory subsystem
|
Simplified software development and maintenance and easy integration into the target SoC |
| …and many more – Download the CEVA-X1643 Product Brief for more information | |
Architectural Highlights
The CEVA-X1643 features a Very Long Instruction Word (VLIW) architecture combined with Single Instruction Multiple Data (SIMD) capabilities. Its 32-bit programming model supports a high degree of parallelism, including the ability to process up to eight instructions per cycle, and 16 SIMD operations per cycle. With a well-balanced pipeline, the CEVA-X1643 can run at over 1 GHz in chips implemented at the 40nm technology node.
The CEVA-X1643 is equipped with a high performance Advanced eXtensible Interface (AXI) based memory sub-system supporting configurable AXI bus widths, parallel read and write transactions, read after write transactions and other advanced capabilities, ensuring target performance is met in a real-life system.
In addition, the CEVA-X1643 supports fully-cached instruction and data subsystems. The combination of this advanced cached architecture with de-facto industry-standard system buses results in higher performance, shorter design cycles, and easy integration into target SoCs.
The CEVA-X1643 includes an innovative Power Scaling Unit (PSU), which provides advanced power management for both dynamic and leakage power. The core supports multiple clock sources and power domains associated with the main functional units, such as the DSP core and the instruction and data caches. The PSU supports multiple operational modes ranging from full operation, debug bypass, and memory retention to complete power shut-off (PSO).
Codecs available directly from CEVA include:
| Vocoders | Audio decoders | Audio encoders | Imaging |
|---|---|---|---|
| G.723 | MP3 | MP3 | JPEG decoder |
| G.729 | MPEG4 AAC-LC | MPEG4 AAC-LC | JPEG encoder |
| G.729.1 | HE-AAC V1 | HE-AAC V1 | |
| G.711 | HE-AAC V2 | ||
| G.726 | WMA9 | ||
| G.727 | WMA10 | ||
| G.168 | RealAudio 8 | ||
| G.161 | RealAudio 9 | ||
| iLBC | RealAudio 10 | ||
| AMR-NB | Dolby Digital (AC3) | ||
| HR | |||
| FR | |||
| AMR-WB | |||
| EVRC | |||
| EVRC-B | |||
| EVRC-C | |||
| QCELP | |||
| SMV |