TeakLite-III

The CEVA-TeakLite-III DSP Core for High-Volume, Cost-Sensitive HD Audio, Voice, and Baseband Applications

The CEVA-TeakLite Family of DSP cores is designed to address the needs of high volume, cost-sensitive markets. Founded on a classic memory-based architecture, the CEVA-TeakLite family combines small die size, high code density, and high processing power.

 

The third generation member of the CEVA-TeakLite family, the CEVA-TeakLite-III is a low-power, native 32-bit, dual MAC, 10-stage pipeline, fixed-point DSP engine that has been specifically designed to be embedded in highly-integrated System-on-Chip (SoC) devices. The CEVA-TeakLite-III is a fully synthesizable (soft core), process-independent design that allows the SoC designer to select the optimal implementation in terms of silicon area, power consumption, and operating frequency.

 

CEVA-TeakLite III Offers Superb Audio DSP Performance

Suitable for the most demanding multi-stream, multi-channel audio processing, the native 32-bit CEVA-TeakLite-III offers superb audio DSP performance. It also offers high performance wireless modem implementations thanks to FFT, Viterbi, and other algorithmic accelerators that are built directly into the core’s Instruction Set Architecture (ISA).

The high-performance, low-power CEVA-TeakLite-III DSP engine forms the basis of the CEVA-TL3210 and CEVA-TL3211 DSP cores. The CEVA-TL3210 offers a wealth of high-end features including a configurable L1 program cache memory and support for industry-standard APB and AHB-Lite system busses. By comparison, the CEVA-TL3211 offers configurable L1 program and data cache memories, support for high-speed AXI system busses, and an integrated Power Scaling Unit (PSU).

CEVA-TeakLite III Supporting Deliverables

 

The CEVA-TL3210 and CEVA-TL3211 DSP cores are supported by a wide range of deliverables, which significantly reduces risk and time-to-market. These deliverables include a complete implementation along with associated hardware and software development tools and verification and simulation environments. CEVA-TL3210 and CEVA-TL3211 designs can also be implemented in an FPGA for prototyping and system integration.

 

The CEVA-TeakLite-III is also backed up by a wealth of software and algorithms. To further reduce the cost, complexity, and risk in bringing products to market, CEVA has established an ecosystem of partners who provide application software, reference designs, complementary IP, design services, and complete solutions based on CEVA’sDSP cores and Platforms and Solutions. Visit our CEVAnet Partners page for more information.

CEVA-TeakLite-III Target Applications

Target applications for the CEVA-TeakLite-III include HD audio, voice, 2G/2.5G/3G wireless baseband, Power Line Communications (PLC), VoIP, and other signal processing for mobile computing devices, wireless handsets, portable media players, Digital TVs (DTVs), Set-top boxes (STBs), Blu-ray Disc players, and more.

Features	Benefits
High performance 1GHz @ 40nm G	High performance makes the CEVA-TeakLite-lll applicable to multiple application domains from audio and voice to baseband
Native 32-bit, Harvard/SIMD architecture DSP Single 32×32-bit multiplier Dual 16×16-bit multipliers 36-bit register files 72-bit accumulation for wide dynamic range	Supported by a broad range of fully-certified HD-Audio and voice codecs
Easy software development Optimizing C compiler Cycle-accurate simulation and graphical profiling of the entire DSP sub-system Macro assembler, linker, and GUI debugger Tight MATLAB bi-directional connectivity (optional)	Smooth C-level software development and easy integration into target SoC reduces risk and time-to-market
…and many more – Download the CEVA-TL3210 and CEVA-TL3211 Product Briefs for more information