+86 21 34616270
info@sitchip.com
徐汇区裕德路168号徐汇商务大厦619室
  • 关于芯桥
  • 新闻
  • 解决方案
  • 产品
    • Synopsys
      • Galaxy平台
      • Design Ware IP
      • Discovery平台
      • System-level Design & Analysis
    • CEVA
    • Arteris
    • VeriSilicon
    • Vivante
    • SILEXICA
  • 服务与培训
    • 专业服务
    • 培训安排
  • 合作伙伴
    • Synopsys
    • CEVA
    • Arteris
    • VeriSilicon
    • Vivante
    • SILEXICA
  • 人才招聘
  • 联系我们
  • About SIT

TeakLite-4

首页 产品 CEVA DSP Cores TeakLite Family TeakLite-4

CEVA-TeakLite-4: A Multifunctional DSP Architecture for High-Performance, Low-Power Audio/Voice/Sensing and Wireless Communication Applications

CEVA-TeakLite-4 DSP LogoThe CEVA-TeakLite Family of DSP cores is designed to address the needs of high volume, cost-sensitive markets. Founded on a classic memory-based architecture, the CEVA-TeakLite family combines small die size, high code density, and high processing power.

 

CEVA-TeakLite-4 DSP Family MembersCEVA-TeakLite-4 DSP Family Members

 

The fourth generation of the CEVA-TeakLite family, the CEVA-TeakLite-4 is a low-power, native 32-bit, variable 10-stage pipeline, fixed-point DSP architecture framework. The CEVA-TeakLite-4 is a fully synthesizable, process-independent design that allows the SoC designer to select the optimal implementation in terms of silicon area, power consumption, and operating frequency.

CEVA-TeakLite-4 V2 architecture further enhances the performance and efficiency of the CEVA-TeakLite-4 family by delivering 30% code size reduction, 20% power consumption reduction and new instructions and mechanisms for audio/voice/wireless standards implementation.

CEVA-TeakLite-4 Target Applications

Thanks to its scalability, the CEVA-TeakLite-4 DSP family is efficiently handling most demanding audio, voice, sensing and wireless connectivity use-cases, whether targeting ultra-low-power always-on functions, advanced multi-microphone voice processing, or high-performance multichannel audio processing and post-processing. CEVA-TeakLite-4 cores are adopted by mobile, home, and automotive chip vendors, ranging from the smallest, lowest-power audio CODEC and voice activation chips, to Baseband, Application Processors and connectivity chips, to high-end audio such as wireless speakers, digital televisions (DTVs), set-top boxes (STBs), game consoles, and more.

 

CEVA-TeakLite-4 Target ApplicationsCEVA-TeakLite-4 Target Applications

 

Always-on User Interface (UI)

Hands-free activation is becoming a ‘must have’ feature in a multitude of devices, primarily smartphones and wearables, and solutions have to operate efficiently and reliably to meet demanding consumer requirements. Be it voice control, gesture control or face unlock, a natural user interface (UI) is expected to be always-on in order to be totally hands-free and therefore must consume very little power. The CEVA-TeakLite-4 offers multi-functional DSP capabilities, making it ideal for implementing always-on solutions that often include intensive signal processing algorithms such as those used for voice recognition and face detection. Furthermore, latest generation power scaling technology of the CEVA-TeakLite-4 V2 enables it to run always-on UI with ultra-low power consumption by shutting down unneeded hardware on a cycle-by-cycle basis. Being CEVA’s smallest DSP core, it also benefits from very low leakage power, which is especially important when implementing always-on functionality, such as that of a voice trigger chip for example.

Sensor-fusion

Sensing is a key feature of smartphones, tablets and IoT devices. Combined processing of sensory data from disparate sources, also known as Sensor Fusion, has proven to provide valuable contextual awareness for a host of user applications. Multiple MEMS sensors such as 9-Axis motion sensors, barometer, thermometer and more call for a high-precision sensor fusion DSP to accurately deduct motion and environmental data, and eliminate false readings. The CEVA-TeakLite-4 boasts a highly optimized arithmetic ISA as well as a rich control ISA that  are efficiently utilized by the compiler as it handles Sensor Fusion code, which often mixes arithmetic and control.

Audio and Voice

Mobile devices like smartphones and tablets are required to handle increasing audio and voice processing requirements, such as multi-microphone beam-forming and noise reduction, wideband voice processing like VoLTE, and long playback time audio, Similarly, automotive infotainments and home-entertainment systems like digital televisions (DTVs), Smart TVs, and Set-Top Boxes (STBs) must support multiple audio and voice standards, advanced audio post-processing, and far-talk voice communication and command. With its dedicated audio and voice ISA, a huge library of certified audio/voice codecs, functions and partner offerings, the CEVA-TeakLite-4 is the most popular audio DSP family.

Wireless connectivity

Combined with the CEVA-Bluetooth hardware and software, the CEVA-TeakLite-4 enables a wide range of wireless applications without requiring an additional CPU. A Smartwatch solution, for example, can use a single Bluetooth-enabled CEVA-TeakLite-4 to run always-on voice activation and voice commands, sensor fusion functionality, audio/voice processing and dual mode Low Energy Bluetooth (also known as Bluetooth Smart Ready) capable of both BLE such as that of Bluetooth Smart, and wireless audio. Given the highly integrated nature of IoT solutions, such a capacity cannot be overestimated. On top of Bluetooth, CEVAnet Partner Program members offer additional wireless technologies for the CEVA-TeakLite-4 that can either be used separately or in a combo solution. For example, a wireless speaker solution combining both a WiFi speaker and a Bluetooth speaker can have both Bluetooth and WiFi audio using a single Bluetooth-enabled CEVA-TeakLite-4 integrated with a CEVAnet WiFi solution.

CEVA-TeakLite 4 Architecture-compliant Cores

The CEVA-TL410, CEVA-TL411, CEVA-TL420, and CEVA-TL421 DSP cores are based on, and compliant to, the high-performance, low-power CEVA-TeakLite-4 DSP architecture.

With a primary target of standalone audio DSP chips used to implement audio CODECs, voice activation, and noise-reduction chips, the ultra-low-power CEVA-TL410 audio DSP core offers the smallest die size with its single 32×32-bit MAC, dual 16×16-bit MACs, and direct memory interface. If higher performance is required, the CEVA-TL411 audio DSP core provides dual 32×32-bit MACs and quad 16×16-bit MACs.

Alternatively, for CPU-centric SoCs, such as the application processors and main SoCs used in smartphones, digital televisions (DTVs), set-top boxes (STBs), and game consoles, the CEVA-TL420 audio DSP augments the features of the CEVA-TL410 with data and instruction cache controllers and a master/slave AXI system interface (the CEVA-TL421 augments the CEVA-TL411 with the same high-end capabilities). All CEVA-TeakLite-4 architecture-compliant cores are fully compatible with each other and with previous generation CEVA-TeakLite family cores.

An audio ISA (instruction set architecture) providing dedicated audio instructions is present in all CEVA-TeakLite-4-based cores. Also, all members of the family include an integrated, second-generation Power Scaling Unit (PSU 2.0) for smart power management.

The CEVA-TeakLite-4 architecture is scalable to support stand-alone audio/voice tasks such as filters, voice pre-processing, audio post-processing, and noise reduction; also for mobile applications such as off-loading the main CPU by performing multi-channel audio decode, transcoding, voice pre-processing, and audio post-processing under the Android operating systems, using the Android Multimedia Framework. The CEVA-TeakLite-4 architecture framework also supports user differentiation to allow expansion for handling proprietary algorithm acceleration and future use-cases.

CEVA-TeakLite 4 Deliverables

 

CEVA-TeakLite-4 block diagramCEVA-TeakLite-4 block diagram

The CEVA-TL410, CEVA-TL411, CEVA-TL420, and CEVA-TL421 DSP cores are supported by a wide range of deliverables, which significantly reduce risk and time-to-market. These deliverables include a complete implementation along with associated hardware and software development tools and verification and simulation environments. CEVA-TeakLite-4-based designs can also be implemented in an FPGA for prototyping and system integration.

 

The CEVA-TeakLite-4 is also backed up by a wealth of software and algorithms. To further reduce the cost, complexity, and risk in bringing products to market, CEVA has established an ecosystem of partners who provide application software, reference designs, complementary IP, design services, and complete solutions based on CEVA’sDSP cores and Platforms and Solutions. Visit our CEVAnet Partners page for more information.

Features Benefits
Small size and ultra-low-power

  • 90K gates area optimized
CEVA-TeakLite-4 DSP cores can be used for applications that are highly sensitive to die-area and power consumption
High-performance

  • Up to 1.5 GHz @ 28nm HPM
CEVA-TeakLite-4 DSP cores support the toughest audio and voice use cases
Native 32-bit, Harvard/SIMD architecture DSP with multiple options:

  • 1/2/4 32×32-bit multipliers
  • 2/4 16×16-bit multipliers
  • 32-bit register file
  • Automatic 16 & 32-bit saturation
  • 72-bit MAC accumulation for wide dynamic range
  • Optional tightly-coupled instruction sets
Supported by a broad range of fully-certified HD-Audio and voice codecs
Easy software development

  • Optimizing C compiler
  • Cycle-accurate simulation and graphical profiling of the entire DSP sub-system
  • Macro assembler, linker, and GUI debugger
  • Tight MATLAB bi-directional connectivity (optional)
Smooth C-level software development and easy integration into target SoC reduces risk and time-to-market
…and many more – Download the CEVA-TeakLite-4 Product Brief

Architectural Highlights

Based on a native 32-bit architecture, different members of the CEVA-TeakLite-4 family can perform one, two, or four 32×32-bit Multiply-Accumulate (MAC) operations and two or four 16×16-bit MAC operations in a single cycle. The CEVA-TeakLite-4 also offers:

  • Enhanced bit-manipulation capabilities for stream processing
  • Up to 5 operations executed in parallel
  • Dedicated single-precision and double-precision FFT instructions
  • Up to 4GW program memory and 4GW data memory (16-bit words)
  • L1 program memory (TCM or cache)
  • L1 data memory (TCM or 2-way, set-associative, hardware-configurable cache)
  • For more information, please contact info@ceva-dsp.com

The CEVA-TeakLite-4 architecture supports an advanced set of digital signal processing instructions as well as general-purpose microprocessor instructions. The CEVA-TeakLite-4’s instruction set and programming model are designed for the straightforward generation of compact and efficient code.

The integrated second generation Power Scaling Unit (PSU 2.0) provides advanced power management including support for clock and voltage scaling.

All members of the CEVA-TeakLite-4 family are compatible with each other and are backward compatible with their predecessors, including the widely adopted CEVA-TeakLite, CEVA-TeakLite-II, CEVA-TeakLite-III, and CEVA-Teak DSP cores. This allows new designs to leverage existing applications and a large installed base of software; it also makes it easy for existing designs to be migrated to a higher performance core.

Codecs available directly from CEVA include:

Vocoders Audio decoders Audio encoders Post-processing
G.723 MP3 MP3 Dolby Mobile 3+
G.729.1 MPEG4 AAC-LC MPEG4 AAC-LC Dolby ProLogic IIx
G.711 HE-AAC V1 HE-AAC V1 Dolby Volume
G.722 HE AAC V2 7.1 SBC DTS Extended Surround (ES)
AMR-NB xxx WMA10 Dolby Digital encoder (DDCE) DTS Neo:6
FR WMA10Pro DTS Transcoder
AMR-WB RealAudio9
SILK RealAudio10
SBC
Dolby TrueHD
Dolby Digital Plus
Dolby Digital (AC3)
Dolby MS10
Dolby MS11
DTS Master Audio
DTS High Resolution
DTS LBR
DTS 96/24
DTS Digital Surround

 

近期文章

  • Synopsys推进虚拟原型技术可支持系统和半导体供应链合作缔造下一代SoC
  • 展讯公司采用Synopsys的ZeBu Server硬件加速器作为其高级移动SoC的标准化开发平台
  • Socionext使用Synopsys TetraMAX II加快测试向量生成并降低测试成本
  • 2016 Synopsys SNUG China(上海站)五月隆重开幕【欢迎报名】
  • Silexica 诚邀您共同迎接多核技术挑战
  • Synopsys SIT Silicon to Software成都研讨会
  • Synopsys推出高性能嵌入式视觉处理器IP
  • Ramon 公司采用CEVA DSP 核 设计空间应用抗核辐照高性能并行处理器
  • Synopsys推出高性能嵌入式视觉处理器IP
  • 新思科技Synopsys虚拟原型设计专著发行超3000本,读者覆盖超1000家公司


上海芯桥信息技术有限公司 SiT (Shanghai) Co., LTD
沪ICP备12038304号